1. Field of the Invention
The present invention relates to a solid state image pickup device represented by a CMOS image sensor, drive method thereof and a camera system.
2. Description of Related Art
In recent years, a CMOS image sensor has been paid attention as a solid state image pickup device (image sensor) to be substituted for CCD.
This is because the CMOS image sensor overcomes various problems of CCD, such as very complicated system caused by the necessity of dedicated processes for manufacturing CCD pixels, the necessity of a plurality of power source voltages for operation, and the necessity to operate by combining a plurality of peripheral IC's.
A CMOS image sensor has a plurality of large merits: manufacturing processes similar to those for a typical CMOS type integrated circuit can be used for manufacturing CMOS image sensors, a single power source can drive a CMOS image sensor, and the number of peripheral IC's can be reduced because analog circuits and logic circuits manufactured by CMOS processes can be mixed on the same chip.
A mainstream of a CCD output circuit is a one channel (1-ch) output using a floating diffusion (FD) amplifier having an FD layer.
In contrast, a mainstream of a CMOS image sensor is a column parallel output type in which each pixel is provided with an FD amplifier, and by selecting each row of a pixel array, outputs of FD amplifiers are read in a column direction at the same time.
It is difficult to obtain sufficient drive ability by an FD amplifier disposed in each pixel, therefore a data rate is required to be lowered. In this context, it is considered that parallel processing is advantageous.
As a CMOS image sensor having this configuration, an image sensor which adds a plurality of consecutive images, stores the added images in a frame memory and outputs a single final image has been proposed (refer to Patent Document 1: Japanese Unexamined Patent Application Publication No. 2006-237772).
FIG. 1 is a diagram showing the structure of an image sensor described in the Patent Document 1.
As shown in FIG. 1, the image sensor 1 includes a pixel portion 2 having pixels 2a arranged in an array shape, a vertical drive circuit 3, an analog/digital (A/D) conversion circuit 4 as a column signal processing circuit, an adder circuit 5, a first sense amplifier 6, a frame memory 7, a second sense amplifier 8, an interface 9, a row select circuit 10 and a control circuit 11.
In the image sensor 1, the vertical drive circuit 3 scans the pixel portion 2, for example, four times. Outputs from the pixel portion 2 are supplied via the AD conversion circuit 4 to the adder circuit 5 which adds the outputs to values read from the frame memory 7 and writes back the addition result to the frame memory 7.
These operations are performed on a column parallel way. In this case, if addition is performed by shifting an origin so as to cancel out detected hand shaking, hand shaking correction is realized.
Further, if weighted addition is performed by changing a storage time of a plurality of scans, a dynamic range expanding operation is realized. If one image is synthesized from four images and outputted, a data amount at an upstream of a camera system can be reduced by about a quarter.
FIG. 2 is a diagram illustrating the operation of the image sensor shown in FIG. 1 while an image is moved.
In the case of moving image, the vertical drive circuit 3 scans the pixel area 2 four times and the row select circuit 10 scans the frame memory 7 four times, whereby one image is formed in the frame memory 7. A timing delay between scans of the pixel portion 2 and a memory portion is a timing delay of time required for AD conversion and calculations. The formed image is then outputted. These operations are repeated.